ADN2817:  Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC (With High Sensitivity Limiting Amp)

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 ...More

ADN2817:  Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC (With High Sensitivity Limiting Amp)

Product Description

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.

The ADN2817/ADN2818 have many optional features available through an I2C® interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.

The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.

Applications

  • SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates
  • Fibre Channel, 2× Fibre Channel, GbE, HDTV, and others
  • WDM transponders
  • Regenerators/repeaters
  • Test equipment

    • Data Sheet, Rev. A, 8/08

    Features

    • Serial data input: 10 Mbps to 2.7 Gbps
    • Exceeds ITU-T jitter specifications
    • Integrated limiting amplifier
      5 mV sensitivity (ADN2817 only)
    • Adjustable slice level: ±100 mV
      (ADN2817 only)
    • Patented dual-loop clock recovery architecture
    • Programmable LOS detect (ADN2817 only)
    • Integrated PRBS generator and detector
    • See Data Sheet for Additional Information

    Diagrams

    ADN2817 Diagram
    Functional Block Diagram for ADN2817

    Specifications

    Data Rate (Gb/s) 2.7Gbps
    Voltage Supply (V) +3.3V
    Power Dissipation (mW) 650mW
    Package 5x5 mm LFCSP
    Jitter Tolerance (Ulpp) 1.0 @ 1 MHz
    Jitter Gen (mUI rms) 1
    Input Sensitivity (mVp-p) 5mV p-p
    Rate Continuous
    Reference Clk Optional
    Data Rate Readback X

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    AD800 -5.5 156 - 80 .9 UI @ 65 kHz - - - 20-Lead SOIC $18.90
    AD807 +5 0.155 170 2 1.0 @ 65 kHz 92 kHz 5 Single 16-Lead SOIC $11.18
    AD808 +5 0.622 400 4 0.6 @ 250 kHz 333 kHz 7 Single 16-Lead SOIC $11.48
    ADN2804 +3.3 0.622 420 3 1.0 @ 250 kHz 71 kHz @ OC12 1 Single 5x5 mm LFCSP $10.00
    ADN2805 +3.3 1.25 390 200 - - - Single 5x5 mm LFCSP $9.33
    ADN2806 +3.3 0.622 360 200 1.0 @ 250 kHz 71 kHz @ OC12 1 Single 5x5 mm LFCSP $9.24
    ADN2807 +3.3 0.622 500 4 1.0 @ 250 kHz 140 kHz @ OC12 1 Multi 7x7 mm LFCSP $11.64
    ADN2811 +3.3 2.7 500 4 1.0 @ 1 MHz 590 kHz @ OC48 2 Single 7x7 mm LFCSP $37.44
    ADN2812 +3.3 2.7 750 6 1.0 @ 1 MHz 490 kHz @ OC48 1 Continuous 5x5 mm LFCSP $54.65
    ADN2813 +3.3 1.25 375 6 1UI @ 637 kHz 71 kHz @ OC12 1 Continuous 5x5 mm LFCSP $19.73
    ADN2814 +3.3 0.675 350 6 1.0 @ 250 kHz 71 kHz @ OC12 1 Continuous 5x5 mm LFCSP $11.64
    ADN2815 +3.3 1.25 300 200 1.0 @ 250 kHz 71 kHz @ OC12 1 Continuous 5x5 mm LFCSP $17.76
    ADN2816 +3.3 0.675 300 200 1.0 @ 250 kHz 71 kHz @ OC12 1 Continuous 5x5 mm LFCSP $10.47
    ADN2817 +3.3 2.7 650 5 1.0 @ 1 MHz 500 kHz @ OC48 1 Continuous 5x5 mm LFCSP $44.26
    ADN2818 +3.3 2.7 600 200 1.0 @ 1 MHz 500 kHz @ OC48 1 Continuous 5x5 mm LFCSP $42.05
    ADN2819 +3.3 2.7 500 4 1.0 @ 1 MHz 590 kHz @ OC48 2 Multi 7x7 mm LFCSP $45.54
    ADN2865 +3.3 2.7 1200