AD6624A:  Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

Designed for multicarrier, multimode receivers, the AD6624A is part of Analog Devices' SoftCell™ Multicarrier transceiver chipset. It is compatible with the latest IF-Sampling analog-to-digital ...More

AD6624A:  Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

Product Description

Designed for multicarrier, multimode receivers, the AD6624A is part of Analog Devices' SoftCell™ Multicarrier transceiver chipset. It is compatible with the latest IF-Sampling analog-to-digital converters including the AD6640, 12-bit and AD6644/AD6645, 14-bit devices. The AD6624 is a four channel (quad) digital receiver signal processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter.

The AD6624A is available in a 196-Lead BGA package.

Applications

  • Wireless Infrastructure: Cellular, PCS, In-Building, WLL
  • GSM, IS-136, AMPS, PHS, EDGE
  • Phased Array Antenna Systems
  • Software Programmable Digital Receivers
  • Communications and Instrumentation

    • Features

    • 100 MSPS Wideband Input (14-Bit)
    • Four Independent Digital Receivers in a Single Package
    • Digital Re-sampling for non-Integer Decimation Rates
    • 3.3 Volt CMOS
    • Programmable Decimating RAM Coefficient FIR Filters
    • JTAG Boundary Scan, Built in Self Test (BIST) Capability

    Diagrams

    AD6624A Diagram
    Functional Block Diagram for AD6624A

    Specifications

    Digital TX/RX RX
    Input Sampling (MSPS) 100MSPS
    Resampler X
    Baseband Interface Serial
    Input Ports 2
    Ouput Ports 4
    Package BGA

    Explore Other Products

    Download this Selection Table
    (pdf, 22,589 bytes)

    Last Updated: 9/2007
    DDCs
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6620 65

    1 Channel

    (main and diversity)

    1 Channel

    2 samples per chip

    1 Channel with FPGA to finish filtering

    2 samples per chip

    1 Channel with FPGA to finish filtering

    2 samples per chip

    		 1 Channel
    AD6624 80

    4 Channels

    2 samples per symbol

    2 Channels

    2 samples per chip

    1 Channel with FPGA for serial to parallel conversion

    2 samples per chip

    1 Channel with FPGA for serial to parallel conversion

    2 samples per chip

    		 4 Channels

    1 sample per chip
    AD6624A 100

    2 Channels with FPGA for serial to parallel conversion

    2 samples per chip
    AD6634 80

    4 Channels

    2 samples per symbol

    2 Channels

    4 samples per chip

    Digital AGC

    2 Channels

    4 samples per chip

    Digital AGC

    2 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    1 sample per chip
    AD6635 80

    8 Channels

    2 samples per symbol

    4 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    4 samples per chip

    Digital AGC

    8 Channels

    1 sample per chip
    AD6636 150

    6 Channels

    4 / 8 samples per symbol

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    1 / 2 / 4 samples per chip
    back to top
    DUCs
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6622

    75

    4 Channels

    Serial output

    2 Channels

    Serial output

    1 Channel

    Serial output

    1 Channel

    Serial output

    4 Channels

    Serial output
    AD6623 104

    4 Channels

    Modulate using I/Q symbols

    Direct modulation xPSK

    Mode switching

    Power Ramping

    2 Channels (real output)

    Serial output

    Includes IIR filter for phase pre-distortion

    2 Channels (real output)

    Serial output

    2 Channels (real output)

    Serial output

    4 Channels

    Serial output

    Power Ramping

    Direct modulation
    AD6633 125

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    Includes IIR filter for phase pre-distortion

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter
    back to top
    Integrated ADC/DDC Receivers
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6652 65

    4 Channels

    2 samples per symbol

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    4 Channels

    1 sample per chip
    AD6653 150

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 4 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor
    AD6654 92.16

    6 Channels

    4 / 8 samples per symbol

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    1 / 2 / 4 samples per chip
    AD6655 150

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 4 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor
    back to top
    QDUCs
    Generic Part # Master Clock (MSPS min) Power Supply Voltage (Vnom) Power Dissipation (mW max) Description
    AD9856 200 Single (+3) 1590 200 MHz Quadrature Digital Upconverter With 12-Bit Data Path
    AD9857 200 Single (3.3 V) 2029 200 MSPS Quadrature Digital Upconverter with 14-bit Data Path
    AD9957 1000 Multi (1.8, 3.3) 1800 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
    back to top
    Pricing, Packaging & Availability

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    **Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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