AD6634:  80 MSPS, Dual-Channel, WCDMA Receive Signal Processor (RSP)

The AD6634 is a two channel (dual) digital Receive Signal Processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a ...More

AD6634:  80 MSPS, Dual-Channel, WCDMA Receive Signal Processor (RSP)

Product Description

The AD6634 is a two channel (dual) digital Receive Signal Processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient-decimating filter. A 16-bit parallel output port provides a means of accommodating high data rate outputs such as in WBCDMA applications.

The AD6634 is part of Analog Devices' SoftCellTM Multi-carrier transceiver chipset designed for compatibility with Analog Devices' family of high sample rate IF sampling ADCs (AD6640/AD6644 12 & 14 bit). The SoftCellTM receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and channel selection. This architecture eliminates redundant radios in wireless base station applications.

High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy reconfiguration for multi-mode applications.

Features

  • 80 MSPS Wide Band Inputs (14 Linear Bit Plus 3 RSSI)
  • Two WCDMA-Digital Receivers In Single Package
  • 16-Bit Parallel Outputs
  • Digital AGC Output Bits for RAKE Receiver
  • Digital Re-Sampling For Non-Integer Decimation Rates
  • Programmable Decimating FIR Filters
  • Flexible Control For Multi-Carrier And Phased Array
  • Programmable Attenuator Control
    for Clip Prevention And External Gain
    Ranging Via Level Indicator
  • 3.3 Volt I/O, 2.5 Volt CMOS Core
  • User Configurable Built In Self Test
    (BIST) Capability
  • JTAG Boundary Scan
  • 156 pin BGA Package

Diagrams

AD6634 Diagram
Functional Block Diagram for AD6634

Specifications

Digital TX/RX RX
Input Sampling (MSPS) 80MSPS
Resampler X
Digital AGC X
Baseband Interface Parallel
Input Ports 2
Ouput Ports 2
Package BGA

Explore Other Products

Download this Selection Table
(pdf, 22,589 bytes)

Last Updated: 9/2007
DDCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6620 65

1 Channel

(main and diversity)

1 Channel

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

 1 Channel
AD6624 80

4 Channels

2 samples per symbol

2 Channels

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

 4 Channels

1 sample per chip
AD6624A 100

2 Channels with FPGA for serial to parallel conversion

2 samples per chip
AD6634 80

4 Channels

2 samples per symbol

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6635 80

8 Channels

2 samples per symbol

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

8 Channels

1 sample per chip
AD6636 150

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
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DUCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6622

75

4 Channels

Serial output

2 Channels

Serial output

1 Channel

Serial output

1 Channel

Serial output

4 Channels

Serial output
AD6623 104

4 Channels

Modulate using I/Q symbols

Direct modulation xPSK

Mode switching

Power Ramping

2 Channels (real output)

Serial output

Includes IIR filter for phase pre-distortion

2 Channels (real output)

Serial output

2 Channels (real output)

Serial output

4 Channels

Serial output

Power Ramping

Direct modulation
AD6633 125

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

Includes IIR filter for phase pre-distortion

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter
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Integrated ADC/DDC Receivers
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6652 65

4 Channels

2 samples per symbol

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6653 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
AD6654 92.16

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
AD6655 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
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QDUCs
Generic Part # Master Clock (MSPS min) Power Supply Voltage (Vnom) Power Dissipation (mW max) Description
AD9856 200 Single (+3) 1590 200 MHz Quadrature Digital Upconverter With 12-Bit Data Path
AD9857 200 Single (3.3 V) 2029 200 MSPS Quadrature Digital Upconverter with 14-bit Data Path
AD9957 1000 Multi (1.8, 3.3) 1800 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
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Pricing, Packaging & Availability

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  • Automotive: -40 to +125 degrees Celsius
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*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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