AD6655:  IF Diversity Receiver

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed ...More

To drive this ADC in DC-coupled applications, we suggest ADA4938-1. To drive this ADC in AC-coupled applications, we suggest AD8352 or AD8376.

AD6655:  IF Diversity Receiver

Product Description

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.

In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.

In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A.

The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

  1. Integrated dual, 14-bit, 150 MSPS ADC.
  2. Integrated wideband decimation filter and 32-bit complex NCO.
  3. Fast overrange detect and signal monitor with serial output.
  4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz.
  5. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
  6. SYNC input allows synchronization of multiple devices.
  7. 3-bit SPI port for register programming and register readback.

Applications

  • Communications
  • Diversity radio systems
  • Multimode digital receivers (3G)
  • TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
  • I/Q demodulation systems
  • Smart antenna systems
  • General-purpose software radios
  • Broadband data applications
  • Data Sheet, Rev. 0, 11/07

    Features

    • SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at 70 MHz @ 150 MSPS
    • SFDR = 80 dBc to 70 MHz @ 150 MSPS
    • 1.8 V analog supply operation

    Integrated dual-channel ADC

    • Sample rates up to 150 MSPS
    • IF sampling frequencies to 450 MHz
    • Internal ADC voltage reference
    • Integrated ADC sample-and-hold inputs
    • Flexible analog input range: 1 V p-p to 2 V p-p
    • ADC clock duty cycle stabilizer
    • 95 dB channel isolation/crosstalk
    • 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply
    • Integer 1-to-8 input clock divider
    • Integrated wideband digital downconverter (DDC)
      - 32-bit complex, numerically controlled oscillator (NCO)
      - Decimating half-band filter and FIR filter
      - Supports real and complex output modes
    • Fast attack/threshold detect bits
    • Composite signal monitor
    • Energy-saving power-down modes

    Diagrams

    AD6655 Diagram
    Functional Block Diagram for AD6655

    Explore Other Products

    Download this Selection Table
    (pdf, 22,589 bytes)

    Last Updated: 9/2007

    DDCs
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6620 65

    1 Channel

    (main and diversity)

    1 Channel

    2 samples per chip

    1 Channel with FPGA to finish filtering

    2 samples per chip

    1 Channel with FPGA to finish filtering

    2 samples per chip

    1 Channel
    AD6624 80

    4 Channels

    2 samples per symbol

    2 Channels

    2 samples per chip

    1 Channel with FPGA for serial to parallel conversion

    2 samples per chip

    1 Channel with FPGA for serial to parallel conversion

    2 samples per chip

    4 Channels

    1 sample per chip

    AD6624A 100

    2 Channels with FPGA for serial to parallel conversion

    2 samples per chip

    AD6634 80

    4 Channels

    2 samples per symbol

    2 Channels

    4 samples per chip

    Digital AGC

    2 Channels

    4 samples per chip

    Digital AGC

    2 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    1 sample per chip

    AD6635 80

    8 Channels

    2 samples per symbol

    4 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    4 samples per chip

    Digital AGC

    4 Channels

    4 samples per chip

    Digital AGC

    8 Channels

    1 sample per chip

    AD6636 150

    6 Channels

    4 / 8 samples per symbol

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    1 / 2 / 4 samples per chip

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    DUCs
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6622

    75

    4 Channels

    Serial output

    2 Channels

    Serial output

    1 Channel

    Serial output

    1 Channel

    Serial output

    4 Channels

    Serial output

    AD6623 104

    4 Channels

    Modulate using I/Q symbols

    Direct modulation xPSK

    Mode switching

    Power Ramping

    2 Channels (real output)

    Serial output

    Includes IIR filter for phase pre-distortion

    2 Channels (real output)

    Serial output

    2 Channels (real output)

    Serial output

    4 Channels

    Serial output

    Power Ramping

    Direct modulation

    AD6633 125

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    Includes IIR filter for phase pre-distortion

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

    6 Channels

    Modulated I/Q data

    VersaCREST™ Crest Reduction Engine

    IF/RF compensation using complex filter

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    Integrated ADC/DDC Receivers
    Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
          1x 3x    
    AD6652 65

    4 Channels

    2 samples per symbol

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    2 Channels with some external filtering

    4 samples per chip

    Digital AGC

    4 Channels

    1 sample per chip

    AD6653 150

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 4 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    AD6654 92.16

    6 Channels

    4 / 8 samples per symbol

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    4 samples per chip

    Digital AGC

    6 Channels

    1 / 2 / 4 samples per chip

    AD6655 150

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 6 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 4 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

    2 x 12 Channels - external Channelization Filters Required

    Fast Level Detect and Power Monitor

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    QDUCs
    Generic Part # Master Clock (MSPS min) Power Supply Voltage (Vnom) Power Dissipation (mW max) Description
    AD9856 200 Single (+3) 1590 200 MHz Quadrature Digital Upconverter With 12-Bit Data Path
    AD9857 200 Single (3.3 V) 2029 200 MSPS Quadrature Digital Upconverter with 14-bit Data Path
    AD9957 1000 Multi (1.8, 3.3) 1800 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
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    Pricing, Packaging & Availability

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    • Pre-Release: The model has not been released to general production, but samples may be available.
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    • Last Time Buy: The model has been scheduled for obsolescence, but may still be purchased for a limited time.
    • Obsolete: The specific part is obsolete and no longer available. Other models listed in the table may still be available (if they have a status that is not obsolete).
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    For detailed drawings and chemical composition please consult our  Package Site

    Pin Count
    Pin Count is the number of pins, balls, or pads on the device. Pin-out diagrams & pin function descriptions may be found in the datasheet.

    Temperature Range
    This is the acceptable operating range of the device. The various ranges specified are as follows:
    • Commercial: 0 to +70 degrees Celsius
    • Military : -55 to +125 degrees Celsius
    • Industrial: Temperature ranges may vary by model. Please consult the datasheet for more information.
    • Automotive: -40 to +125 degrees Celsius
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    *The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
    **Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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