ADSP-TS101S:  300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

The ADSP-TS101S is the first member of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute ...More

ADSP-TS101S:  300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

Product Description

The ADSP-TS101S is the first member of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI’s TigerSHARC processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS101S features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC processor to offer unrivaled DSP performance. At a 300 MHz clock rate, the ADSP-TS101S offers the industry’s highest 16-bit fixed-point performance and a 32-bit floating 1024-point complex FFT time of 32.5 microseconds.

ADSP-TS101S Performance:

  • High performance 300 MHz, 3.3 ns instruction rate DSP core
  • Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle
  • Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (1800 MFLOPS or 7.2 GOPS performance)
  • 8-cycle instruction pipeline; 3-cycle fetch pipe and 5-cycle execution pipe
  • Parallelism allows the execution of up to four 32-bit instructions per cycle

    • The ADSP-TS101S is available in both 19mm X 19mm and 27mm X 27mm inexpensive, plastic ball-grid array packages. The TigerSHARC is available for general purpose sampling today.

    Features

    • Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
    • High performance 300 MHz, 3.3 ns instruction rate DSP core
    • 6 Mbit on-chip SRAM internally organized in three banks with user-defined partitioning
    • 14 channel, zero overhead DMA controller
    • Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC to offer complete base band processing
    • Three internal 128-bit wide internal buses providing a total memory bandwidth of 14.4 Gbytes per second
    • Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
    • Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
    • Assembly and C language programmability

    Diagrams

    • Enlarge
    ADSP-TS101S Diagram
    Functional Block Diagram for ADSP-TS101S

    Markets & Applications

    • Video and communications markets including the 3G cellular and 802.16 broadband wireless base stations
    • Industrial and Instrumentation including military and medical

    Specifications

    Clock Speed (MHz) 300MHz
    MMACs 2400
    On-Chip Memory (Mbit) 6Mbit
    External Memory (Mbit) 32/64
    Parallel Bus Yes
    Core Voltage (V) 1.2V
    Package 19 x 19 BGA,27 x 27 BGA
    Pricing, Packaging & Availability

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    *The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
    **Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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