ADSP-TS201S:  500/600 MHz TigerSHARC Processor with 24 Mbit on-chip embedded DRAM

The ADSP-TS201S is one of the members of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute ...More

GT-3U-cPCI Board from BittWare, featuring multiple ADSP-TS201 TigerSHARC Processors, provides flexibility and performance in high-end military applications.

ADSP-TS201S:  500/600 MHz TigerSHARC Processor with 24 Mbit on-chip embedded DRAM

Product Description

The ADSP-TS201S is one of the members of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI's TigerSHARC Processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS201S features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC Processor to offer unrivaled DSP performance. At a 600 MHz clock rate, the ADSP-TS201S offers the industry's highest 16-bit fixed-point and 32-bit floating point performance. The ADSP-TS201S has a 1024-point complex FFT time of 16.8 microseconds and provides 1500 MFLOPs per watt.

ADSP-TS201S Performance:
- High performance 600 MHz, 1.67 ns instruction rate DSP core
- Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle
- Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (3.6 GFLOPS or 14.4 GOPS performance)
- 2-cycle, interlocked execution pipe
- Parallelism allows the execution of up to four 32-bit instructions per cycle

The ADSP-TS201S is available in a 25x25mm inexpensive, BGA package. The TigerSHARC Processor is available for general purpose sampling today.

Features

  • Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
  • High performance up to 600 MHz, 1.67 ns instruction rate DSP core
  • 24 Mbit on-chip embedded DRAM internally organized in six banks with user-defined partitioning
  • Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC Processor to offer complete baseband processing
  • 14 channel, zero overhead DMA controller
  • Four internal 128-bit wide internal buses providing a total memory bandwidth of 38.4 Gbytes per second
  • Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
  • Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
  • Assembly and C language programmability

Diagrams

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ADSP-TS201S Diagram
Functional Block Diagram for ADSP-TS201S

Markets & Applications

  • Video and communications markets including the 3G cellular and 802.16 broadband wireless base stations
  • Industrial and Instrumentation including military and medical

Specifications

Clock Speed (MHz) 600MHz
MMACs 4800
On-Chip Memory (Mbit) 24Mbit
External Memory (Mbit) 32/64
Parallel Bus Yes
Core Voltage (V) 1.2V
Package 25 x 25 BGA
Pricing, Packaging & Availability

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*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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