AD6633:  Multi-channel (Digital) Transmit Signal Processor (TSP) with VersaCREST™ Crest Reduction Engine

The AD6633 is a multi-channel, wide-bandwidth (Digital) Transmit Signal Processor (TSP) with VersaCREST™ crest reduction engine. It processes digital baseband input data and generates wideband, real ...More

AD6633:  Multi-channel (Digital) Transmit Signal Processor (TSP) with VersaCREST™ Crest Reduction Engine

Product Description

The AD6633 is a multi-channel, wide-bandwidth (Digital) Transmit Signal Processor (TSP) with VersaCREST™ crest reduction engine. It processes digital baseband input data and generates wideband, real or complex output data. It drives Intermediate Frequency (IF) sampling Digital to Analog Converters (DACs) at sample rates up to 125 Mega Samples Per Second (MSPS). Up to six wideband modulated carriers per package can be achieved from a single output port. Devices may be connected together for additional channels by using multiple packages. Interpolation, anti-imaging filtering, all pass equalization, and NCO tuning functions are combined in a single, cost-effective device which includes the VersaCREST™ crest factor reduction engine.

Each VersaCREST™ wideband channel contains a peak-to-average compensation block that reduces Power Amplifier (PA) requirements. By minimizing infrequent peaks in Code-Division Multiple-Access (CDMA) signals, a PA with one-half to one-quarter the previously necessary power capacity can be used. This is done within standard signal quality requirements, and significantly lowers system cost.

For more information on the Digital Up/Down Converters (VersaCOMM®) Family of Products, visit the home page.

VersaCREST is a trademark of Analog Devices Inc.

Features

  • 4 or 6 wideband digital upconverter channels
  • VersaCREST™ crest reduction engine reduces demands on external power amplifiers
  • One 20-bit complex input port (I/Q interleaved), shared among 4 or 6 processing channels
  • Two 18-bit output ports for parallel I and Q, or interleaved I and Q on a single port
  • All-pass phase equalizer filters (meets cdma2000 requirements)
  • Programmable RAM coefficient FIR filters (RCF) with resampling
  • FIR interpolating filters and Fifth-order interpolating CIC filter
  • Full complex NCO, 32-bit tuning resolution (fine), worst spur better than - 105 dBc
  • Complex FIR filter for frequency equalization
  • Power monitoring and output Automatic Gain Control
  • 16-bit/8-bit MicroPort or SPI/SPORT compatible serial port
  • 3.3 V I/O and 1.8 V core supplies

Diagrams

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  • Symbols and Footprints
AD6633 Diagram
Functional Block Diagram for AD6633

Specifications

Digital TX/RX TX
Input Sampling (MSPS) 125MSPS
Resampler X
Digital AGC X
Baseband Interface Parallel
Input Ports 1
Ouput Ports 2
Package BGA

Explore Other Products

Download this Selection Table
(pdf, 22,589 bytes)

Last Updated: 9/2007
DDCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6620 65

1 Channel

(main and diversity)

1 Channel

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

 1 Channel
AD6624 80

4 Channels

2 samples per symbol

2 Channels

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

 4 Channels

1 sample per chip
AD6624A 100

2 Channels with FPGA for serial to parallel conversion

2 samples per chip
AD6634 80

4 Channels

2 samples per symbol

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6635 80

8 Channels

2 samples per symbol

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

8 Channels

1 sample per chip
AD6636 150

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
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DUCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6622

75

4 Channels

Serial output

2 Channels

Serial output

1 Channel

Serial output

1 Channel

Serial output

4 Channels

Serial output
AD6623 104

4 Channels

Modulate using I/Q symbols

Direct modulation xPSK

Mode switching

Power Ramping

2 Channels (real output)

Serial output

Includes IIR filter for phase pre-distortion

2 Channels (real output)

Serial output

2 Channels (real output)

Serial output

4 Channels

Serial output

Power Ramping

Direct modulation
AD6633 125

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

Includes IIR filter for phase pre-distortion

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter
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Integrated ADC/DDC Receivers
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6652 65

4 Channels

2 samples per symbol

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6653 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
AD6654 92.16

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
AD6655 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
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QDUCs
Generic Part # Master Clock (MSPS min) Power Supply Voltage (Vnom) Power Dissipation (mW max) Description
AD9856 200 Single (+3) 1590 200 MHz Quadrature Digital Upconverter With 12-Bit Data Path
AD9857 200 Single (3.3 V) 2029 200 MSPS Quadrature Digital Upconverter with 14-bit Data Path
AD9957 1000 Multi (1.8, 3.3) 1800 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
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Pricing, Packaging & Availability

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  • Automotive: -40 to +125 degrees Celsius
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*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples iinto your cart to check sample availability.

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