FAQs: Direct Digital Synthesis (DDS)
Last Updated: 4/2007
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Features - Functions
- What type of frequency sweeping is available?
- What type of automatic frequency sweeping modes does each of your DDS parts support?
- I'm not using all the blocks of the AD9858. What do I do with the unused inputs of these sections?
- What causes a Quadrature Digital Upconverter (AD9856, AD9857) to go into a CIC overflow condition?
Frequency Sweeping
Q: What type of frequency sweeping is available?
A: There are several types of frequency sweeping available:
- Linear ramp with defined endpoints - (commonly called ramped FSK). The user is able to program a beginning and terminating frequency. The user can then specify an incremental frequency and the rate at which to increment the frequency. Upon reaching the terminating frequency the device may either hold the terminating frequency value (standard), or return to the starting frequency instantaneously (return-to-zero).
- Linear sweep with no defined endpoints - As with ramped FSK, the user can specify an incremental frequency value and the rate at which to increment the frequency. However, as there are no defined endpoints, once the sweep begins, it only stops when the user indicates a stop, either via a pin control (HOLD pin on AD9852) or by writing to one of the registers a zero value. The user can also clear the "Linear Sweep Enable" bit in the control register for the device, but this clears all information from the linear sweep registers, and the frequency immediately returns to the value stored in the frequency tuning word of the active profile.
- RAM modes of operation - The AD9953 and AD9954 include a 1024x32 RAM which can be programmed by the user. The values stored in the RAM can be used as frequency tuning words. Please see the AD9953 or AD9954 datasheets for more details of the RAM sweep modes of operation.
Q: What type of automatic frequency sweeping modes does each of your DDS parts support?
A:
| Linear Sweep (defined endpoints – Ramped FSK) |
Linear Sweep (no defined endpoints) |
RAM mode (user defined) |
No Automatic Frequency Sweep | |
|---|---|---|---|---|
| AD9850 | Must be done by writing successive FTW to the part | |||
| AD9851 | Must be done by writing successive FTW to the part | |||
| AD9852 | Yes | Yes | Has a hold pin | |
| AD9854 | Yes | Yes | Has a hold pin | |
| AD9858 | Yes | Does not have a hold pin | ||
| AD9951 | Must be done by writing successive FTW to the part | |||
| AD9952 | Must be done by writing successive FTW to the part | |||
| AD9953 | Yes | |||
| AD9954 | Yes | Yes |
Phase Offset and Adjustment
Q: How do I change the phase of my output signal?
A: To change the phase offset of the DDS output signal, write a value to the phase offset register. Upon issuing an I/O update (FUD), the part will add the phase offset to the current value of the phase accumulator. This phase change occurs in phase continuous manner.
Q: Are frequency changes of a DDS phase coherent?
A: No, the frequency changes of a DDS are phase continuous, but not phase coherent. When a new frequency is programmed into the DDS, the next phase will simply be incremental with respect to the last phase value in the phase accumulator, and therefore the output sinewave will be phase continuous. That is, there will be no phase discontinuity, or glitch. You cannot switch from F1 to F2, then back to F1 and expect to be in the same phase as F1 was in originally.
Amplitude Modulation
Q: How do I perform amplitude modulation on the output?
A: Some of the ADI DDS products have a scale factor or digital multiplier between the DDS core and the DAC. On these parts amplitude modulation can be achieved by writing a digital value to the appropriate register (amplitude scale factor). This value can be updated at the necessary modulation rate. The user must assure that the part can accept data at the required update rate via its serial or parallel I/O interface.
Q: How can I control the envelope of the output?
A: There are two methods for enveloping short output bursts: automatic output shift keying (OSK), and manual OSK. In automatic mode, the user can program a maximum amplitude scale factor (<=1). When the OSK pin is brought high, the part will ramp from a scale factor of zero to the set value in an interval defined by the value in the ramp rate register. When the pin is brought low, the amplitude is ramped back down at the same rate to zero. In manual mode, the user can write and update scale factors to increase or decrease the amplitude during the burst. The user must assure that the part can accept data at the required update rate via its serial or parallel I/O interface.
Comparators
Q: How do I use a DDS for a clock driver?
A: To use a DDS as a clock driver, the output sinewave must be converted to a rectangular wave with fast edge transitions (high slew rate). In order to do this, it is necessary to pass the AC output signal through a high-speed comparator, with an output of the correct voltage level.
Many of the ADI DDSs have integrated high-speed comparators in order to make clock signal generation simple. It is also always possible to use an external, high-performance, high-speed comparator from ADI. But, in all cases – don't forget the low pass (band pass) filter.
Please refer to Application Notes AN-823, "Direct Digital Synthesizers in Clocking Applications" and AN-837, "DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance" for more detailed information.
General DDS
Q: I'm not using all the blocks of the AD9858. What do I do with the unused inputs of these sections?
A: These inputs become high impedance noise. To keep noise from coupling in on these pins, we recommend placing a 0.1µF cap to AGND on each of the inputs when unused.
Q: What causes a Quadrature Digital Upconverter (AD9856, AD9857) to go into a CIC overflow condition?
A: The most likely causes of a CIC overflow condition are as follows:
- There is excessive jitter on the REF CLK (This can be exacerbated when you are using the internal REF CLK multiplier).
- The REF CLOCK multiplier PLL becomes unlocked while TX enable is high.
- Profiles were changed (by pins PS0, PS1) while TX enable was high.
Both the AD9856 and the AD9857 can exhibit a CIC overflow condition if any of the above occur. The AD9857 has a CIC overflow pin (pin 69); if this pin begins to toggle (anything but staying low), a CIC overflow has occurred. The AD9857 also allows the lock status of the PLL to be monitored (pin 68). If the PLL is becoming unlocked during TX operation, then there is probably excessive jitter on the external reference signal.
Evaluation Board & Interface
- Should I separate digital and analog ground planes on my evaluation board?
- Do you recommend a linear or switching power supply?
- I have limited power to supply to the part. What can I do to reduce the power consumption of the device and thus ensure that my supply is adequate?
- What is the effect of increasing my supply voltage beyond the nominal recommended value?
- What layout recommendations do you have for the power supply pins of the DDS device?
- Can I use the same power supply for AVDD and DVDD?
- What is the ratio between the analog and digital currents drawn by the DDS devices?
- What are the proper logic input levels for the DDS parts?
- What are the advantages and disadvantages of serial and parallel mode?
- Can I read back data at the same rate that I can write the data to the DDS device?
- What logic families can interface with our parts?
- What is the maximum speed I can write to the part?
- I would like to update the FTW of my DDS, but only a single byte of the FTW needs to change. Can the frequency tuning word of a DDS be partially updated a byte at a time?
- How can I synchronize multiple DDS parts?
- What is the maximum speed I can write to the part?
- Can I gate the REF CLK on and off?
- What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
- What is the effect of REF CLK jitter on the DDS?
- What is the proper termination for the DAC outputs for the DDS products?
- Why can't I see a signal at the output of my DDS when it is unterminated? (I'm setting everything correctly, but I'm just probing the output pins of the DDS which have nothing connected to them.)
- I am having problems getting my evaluation software to see my evaluation board; what should I do to correct the problem?
- Is all DDS software supplied by Analog Devices compatible with all WinXX versions?
- Can the DDS evaluation boards be integrated directly into a system project?
- Should I separate digital and analog ground planes on my evaluation board?
Power Supplies
Q: Should I separate digital and analog ground planes on my evaluation board?
A: Separating analog and digital ground planes is a good idea, but not always necessary. It is often very difficult to implement properly, so one should proceed with caution. All of our evaluation boards use a common analog and digital ground plane, but with separate power supply planes.
Separating digital and analog ground planes will help keep digital switching transient ground currents from contaminating the analog circuitry. In many of our earlier products (AD9850, AD9851, AD9852, AD9853, AD9854, AD9856, AD9857) the benefit gained from separating ground planes was minimal at best. However, in later products, the AD9858, AD9951/52/53/54 and AD9859, separating the ground planes can help to isolate the SYNC-CLK from the analog output.
Q: Do you recommend a linear or switching power supply?
In the past a linear supply was greatly preferred to a switching supply because of the presence of switching transients on the dc output of the switchers. Switching supplies have made great improvements in terms of switching noise suppression over the past few years. The most important consideration is adequate power supply bypassing directly at the device pins.
Q: I have limited power to supply to the part. What can I do to reduce the power consumption of the device and thus ensure that my supply is adequate?
A: Most power intensive features, such as the inverse sinc filter (if included on the device) can be individually powered down. If amplitude flatness across the Nyquist region is not a requirement in your application, then you could power it down to conserve power. If the comparator is not needed, powering it down will also help reduce power.
Finally, if things are really tight, you might look at the possibility of reducing the system clock frequency to the minimum necessary (say, 2.5 times the maximum output frequency). While this will reduce the power consumption, it should only be done if absolutely necessary, because oversampling usually improves the output spectral performance.
Q: What is the effect of increasing my supply voltage beyond the nominal recommended value?
A: Increasing the supply voltage (within the functional limits) will increase the current drawn by the part, which means the power dissipation will increase proportional to the square of the voltage. The speed of the digital section of the device will increase slightly, but the data sheet specified performance of the device will be met at the nominal voltage. In any case, thermal dissipation limits for the device must not be exceeded. This means that the junction temperature must not exceed 150C.
The device should be operated within the nominal voltage plus or minus the specified variance (usually 5%). In all cases the absolute maximum voltage limit must not be approached or exceeded. You will probably blow up your part. Boom!
Q: What layout recommendations do you have for the power supply pins of the DDS device?
A: It is important that all supply pins (GND, AVDD, DVDD) connect to their respective GND or POWER plane with the shortest amount of trace length. This will reduce the total series inductance.
Equally important is to connect bypass chip-capacitors as close as possible to each and every power pin. Typically, we recommend 0.01µF for these capacitors. This will provide a good AC ground at the power pins for higher frequencies in order to minimize noise coupling from the part to the power supply rail, and vice versa.
Q: Can I use the same power supply for AVDD and DVDD?
A: A single supply can definitely power both AVDD and DVDD. However it may not provide the best isolation between the analog and digital circuitry which may increase the noise coupling. We typically recommend going by our evaluation board layout as the test bed for the user. Best engineering practice dictates good AC bypassing at each individual device pin, and providing adequate trace size to reduce IR drops to minimal amounts (e.g. – use power planes).
Q: What is the ratio between the analog and digital currents drawn by the DDS devices?
A: Typically, the analog current is 10% to 30% of the total current when the device is running at the MAX System CLK rate. In some DDSs (AD9852/54), it also depends on which options or features are enabled (inverse SINC, amplitude scale factor, etc.). The analog current is mainly biasing current, therefore the current does not change much with the System CLK rate, unlike the digital current which is proportional to the System CLK rate. If the System CLK is quite low the analog current may dominate the total current.
I/O Interface
Q: What are the proper logic input levels for the DDS parts?
A: The logic I/O level high should not exceed the digital power supply voltage, DVDD. Any voltage or logic level beyond this will cause the ESD protection diodes to begin to turn on, which may couple unwanted digital noise onto the power pins.
Q: What are the advantages and disadvantages of serial and parallel mode?
A: Serial mode offers the advantage of fewer traces on the pc board, and fewer pins on the devices. Parallel offers the advantage of transferring 8 data bits per I/O clock cycle, but at the disadvantage of many more pins required on the devices.
On some of the DDS devices (AD9852/54/58) the parallel port offers the advantage of addressing single bytes in the device register set, whereas the serial port requires all of the bytes of a multibyte register to be loaded at one time.
Overall, the parallel mode offers the advantage of faster loading of the registers, but with the disadvantage of requiring more interconnect traces. The serial mode offers simplicity, but with less speed.
In some cases, an application may require a data update rate which can be achieved while using the parallel mode, but which could not be accomplished while using the serial mode due to its slower update rate.
Q: Can I read back data at the same rate that I can write the data to the DDS device?
A: Maybe. However, it is not guaranteed. The readback capability was added as a diagnostic tool only. It has not been specified for speed.
Q: What logic families can interface with our parts?
A: The logic level I/O requirements of the various DDS parts are determined by the operating voltages of the devices. The logic inputs and outputs are CMOS levels, and can be interfaced with any logic families which operate at the same power supply voltage. I/O logic should be selected from an appropriate CMOS logic family. The speed of the family must be adequate for the speeds to be employed in the application.
The AD9851/52/53/54 and AD9859, which require a 1.8V power supply, can be operated with logic operating between 1.8 – 3.3V, by applying the desired voltage within this range to the I/O supply pin of the device.
Q: What is the maximum speed I can write to the part?
A: The maximum speed at which a given device can be written to is given in the device's data sheet.
The AD9850 and AD9851 are spec'd in terms of clock and data setup-and-hold times.
The AD9852/54/58 parallel port can read data at up to approximately 100MHz (byte rate), while the serial port operates at up to 10Mbits/s.
The AD9951/52/53/54 and AD9859 have only a serial I/O port. This port, however, can be written to at a rate of 25Mbits/s.
Q: I would like to update the FTW of my DDS, but only a single byte of the FTW needs to change. Can the frequency tuning word of a DDS be partially updated a byte at a time?
A: On some of the ADI DDSs which have a parallel data interface and which are being used in parallel mode it is possible to address individual bytes in the frequency register. However, the serial mode interface does not support sub-register (individual byte) addressing of the FTW.
Timing
Q: How can I synchronize multiple DDS parts?
A: Two application notes are currently available from Analog Devices that guides the user through the synchronization of multiple DDS parts. The AN-587 discusses the synchronization of the AD9850/9851 synthesizers, while the AN-605 gives synchronization instructions for the AD9852/9854 parts. Otherwise, see product datasheet for information on multiple device synchronization.
Q: What is the maximum speed I can write to the part?
A: The maximum speed at which a given device can be written to is given in the device's data sheet.
The AD9850 and AD9851 are spec'd in terms of clock and data setup-and-hold times.
The AD9852/54/58 parallel port can read data at up to approximately 100MHz (byte rate), while the serial port operates at up to 10Mbits/s.
The AD9951/52/53/54 and AD9859 have only a serial I/O port. This port, however, can be written to at a rate of 25Mbits/s.
Q: Can I gate the REF CLK on and off?
A: Yes. This is a valid "sleep" strategy. Gating off the REF CLK between operating periods will significantly reduce the idling current.
The DDS logic is CMOS, and when it is not clocking, the current is greatly reduced. On the AD9858 (because the DAC is implemented in bipolar), the analog bias currents do not reduce when the ref clock is gated off.
Q: What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
A: Typically, the first thing to happen when you exceed the maximum CLOCK RATE is a violation of the thermal specifications of the device. The increase in clock rate causes an increase in power dissipation which raises the die temperature. This temperature rise can be calculated by the following formula: Tdie = Tambient + PWR(Theta JA). You should not exceed the maximum junction temperature specification, which is typically 150C.
Overclocking also may result in spectral degradation, due to the violation of internal timing requirements (internal setup and hold times) which are thermally sensitive. If you over clock an ADI DDS part, you do so at your own risk. ADI does not guarantee performance or lifespan of the device.
Q: What is the effect of REF CLK jitter on the DDS?
A: REF CLK jitter will directly affect the DDS. The DDS output is sampled by the REF CLK, and therefore the REF CLK jitter determines the quality of the output signal. It directly affects the jitter characteristics of the DDS output.
If the REF CLK multiplier (PLL) is utilized, then the PLL (because its loop bandwidth acts as a bandpass filter) helps to filter out frequency components of the REF CLK that are outside of the loop bandwidth of the PLL.. However, using the REF CLK multiplier will increase the effective noise on the REF CLK within the loop bandwidth of the PLL (typically a few hundred kHz). The increase of noise within the loop bandwidth will follow the formula of dB = 20log x, where x is the REF CLK multiplication value.
Output Termination
Q: What is the proper termination for the DAC outputs for the DDS products?
A: The DAC outputs should be terminated with the proper load impedance in order to limit the output voltage swing so that it is within the voltage compliance limits of the output stage. Both DAC outputs (true and complementary) should be terminated with the same resistance for best SFDR performance, and to limit harmonic distortion at higher output frequencies. In most cases this should be 50 ohms.
Q: Why can't I see a signal at the output of my DDS when it is unterminated? (I'm setting everything correctly, but I'm just probing the output pins of the DDS which have nothing connected to them.)
A: All ADI DDS ICs have DACs with current-mode outputs. It is necessary to convert the current to a voltage by passing the output through an appropriate value of resistor before a voltage signal can be measured. Also, a balanced-to-balanced, or balanced-to-unbalanced transformer may be used. The transformer must be center-tapped on the DDS side in order to provide a current path for the DAC outputs.
The output from the DDS DAC is a pair of complementary currents, set by the external Iset resistor to a suitable value. This current is usually 10mA, or sometimes 20mA. This is a fixed current, which is steered between the Iout and Iout_bar DAC output pins according to the digital code applied to the DAC at the instant. Full scale positive results in all of the current coming out of the Iout pin, and none out of the Iout_bar pin. Full scale negative is the opposite – all of the current coming out of the Iout_bar pin, none out of the Iout pin. Midscale on the DAC results in equal amounts of current coming from both pins simultaneously. The sum of the currents at any instant is always equal to the Iset current.
The fact that the DDS outputs are current sources means that the outputs must always have a current path to ground (or VCC in some DDSs). The current sources have a voltage compliance of only about 1V. This means that when Iset is 20mA, the maximum resistive load is 50 ohms. The need for a current path also explains why a center-tapped transformer is usually used when a balanced output is desired.
Note: The AD9852 and AD9854 also have an output scale factor multiplier which defaults to 0000. This will also prevent you from seeing any output signal until the scale factor is bypassed or set to some non-zero value.
Software
Q: I am having problems getting my evaluation software to see my evaluation board; what should I do to correct the problem?
A: First, be sure that the evaluation board is powered-up properly before launching the evaluation software, as in most cases the evaluation software will not be able to see the evaluation board without proper power on the board.
Faulty or inadequate printer cables have been a common source of problems with our evaluation boards. Be sure that you use an IEEE-1284 or compatible printer cable, preferably 6 ft. or shorter. Some printer cables which are not IEEE-1284 may not have all of the pins connected, and may not have adequate shielding to prevent crosstalk and noise problems.
Be sure that the evaluation software has the correct port address for the parallel port. Your computer may have more than one parallel port installed. If you launched the evaluation software before the board was powered on, it may have set the wrong port address. This can be set manually from the evaluation software in order to correct this problem.
The newer MS operating systems (WinNT, Win2000, WinXP) do not allow user software to directly address the ports on the PC. This means that a system level driver must do this. Our evaluation software must install a suitable driver in order to communicate with the parallel port. This can sometimes fail during the installation of the software, depending on the exact configuration of the OS and the user's privileges. The user must have admin privileges in order to properly accomplish this installation.
Q: Is all DDS software supplied by Analog Devices compatible with all WinXX versions?
A: All software has recently been updated to work on all Win9x, WinNT, Win2000, and WinXP operating systems. Be sure to uninstall any previous software versions before installing a new version. Remember that WinNT, Win2000, and WinXP require that you have admin privileges in order to install our software. Also, please be aware that the installation of our evaluation software may require multiple reboots in order to properly install the required device driver and properly register the software. Pay close attention to the prompts!
General
Q: Can the DDS evaluation boards be integrated directly into a system project?
A: While the DDS evaluation boards do allow a good exercise of the functionality of the DDS part, the evaluation board is designed only to test the DDS for the suitability in the customer's application. The evaluation boards are not intended for direct integration into customer projects or products. The boards are NOT designed or assembled to meet any military specifications.
Q: Should I separate digital and analog ground planes on my evaluation board?
A: Separating analog and digital ground planes is a good idea, but not always necessary. It is often very difficult to implement properly, so one should proceed with caution. All of our evaluation boards use a common analog and digital ground plane, but with separate power supply planes.
Separating digital and analog ground planes will help keep digital switching transient ground currents from contaminating the analog circuitry. In many of our earlier products (AD9850, AD9851, AD9852, AD9853, AD9854, AD9856, AD9857) the benefit gained from separating ground planes was minimal at best. However, in later products, the AD9858, AD9951/52/53/54 and AD9859, separating the ground planes can help to isolate the SYNC-CLK from the analog output.
Ref Clock & Other
- What type of signal source is recommended?
- How does the REF CLK performance affect the DDS performance?
- What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
- Why does spectral performance degrade when using larger values of multiplication on the clock multiplier?
- What is the required duty cycle of the REF CLK signal?
- If the port has a differential REF CLK, and I want to use a single-ended clock, what do I do with the other differential input?
- If I violate the proper logic level of the REF CLK (that is, underdrive or overdrive it), what can I expect?
- Which option is better for the REF CLK signal: single-ended or differential mode?
- Can I gate the REF CLK on and off?
- What is the effect of REF CLK jitter on the DDS?
- Are there any specific recommendations for material in the vias of the circuit board for the thermally enhanced package styles in which some ADI DDSs are available?
- I have limited experience working with thermally enhanced packages. Where can I get information concerning the proper techniques for soldering and assembly?
- I need to operate my DDS part above the rated temperature range. Can you give me any reliability data?
- Are any of your DDS products space qualified?
- What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
- Why did the model numbers change on the AD9852 and AD9854 products? I thought they were available in the ASQ package.
Signal Source
Q: What type of signal source is recommended?
A: Crystal or SAW oscillators do a very good job for a REF CLK. The performance of the DDS system is limited by the quality of the oscillator. The better the performance of the oscillator, the better the DDS performance.
We have recommended the following manufacturers of oscillators:
Ecliptek | Epson | Sirenza | Connor-Winfield | Wenzel | Valpey-Fisher
Q: How does the REF CLK performance affect the DDS performance?
A: Since the REF CLK is the source for the DAC sampling, any frequency drift, timing jitter, or excessive phase noise that is associated with the REF CLK will be transferred in some degree to the DAC output. Therefore, the better the REF CLK, the better the DDS performance.
Q: What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
A: Typically, the first thing to happen when you exceed the maximum CLOCK RATE is a violation of the thermal specifications of the device. The increase in clock rate causes an increase in power dissipation which raises the die temperature. This temperature rise can be calculated by the following formula: Tdie = Tambient + PWR(Theta JA). You should not exceed the maximum junction temperature specification, which is typically 150C.
Overclocking also may result in spectral degradation, due to the violation of internal timing requirements (internal setup and hold times) which are thermally sensitive. If you over clock an ADI DDS part, you do so at your own risk. ADI does not guarantee performance or lifespan of the device.
Q: Why does spectral performance degrade when using larger values of multiplication on the clock multiplier?
The REF CLK multiplier is implemented by a PLL circuit. The phase noise performance of a PLL is determined by the multiplication ratio, and the loop filter performance. Within the loop bandwidth of the REF CLK multiplier, any noise that is present on the REF CLK will be gained up in proportion to the multiplication value (4x to 20x). This inherent effect degrades narrowband SFDR performance of the DDS, although it does not necessarily degrade the wideband SFDR. The formula for signal degradation within the PLL loop bandwidth is given by db = 20 log x, where x is the multiplication value. The loop bandwidth is typically a few hundred kHz.
Q: What is the required duty cycle of the REF CLK signal?
This information can be found in the data sheet. It is typically 40-60%.
Interfacing
Q: If the port has a differential REF CLK, and I want to use a single-ended clock, what do I do with the other differential input?
A: In single-ended mode, we recommend tying the REF CLKB input to GND or VCC (it doesn't matter which). If the input floats, noise on that node could cause erratic clocking and induce additional noise on the clocking signal. It is never a good idea to leave a CMOS input floating.
Q: If I violate the proper logic level of the REF CLK (that is, underdrive or overdrive it), what can I expect?
A: If you overdrive the REF CLK input(s), you may forward bias diodes that are present at the input for ESD protection. These diodes terminate to VCC and GND; therefore forward biasing them could dump digital noise on power or GND busses. It is important to maintain a good AC ground at both GND and all power pins.
If you underdrive the REF CLK input(s) you may experience intermittent problems such as glitches on the DAC output; or the part may not respond at all. The presence of a sufficient REF CLK signal on the device can be quickly checked by monitoring the power supply current (digital). If the input REF CLK circuitry is not switching, the total current will be significantly reduced. This is because the DDS consists of mostly CMOS digital circuitry which does not draw much current when not switching.
Q: Which option is better for the REF CLK signal: single-ended or differential mode?
A: In most cases differential clock mode is recommended. This is because of the superior noise performance associated with differential signals, if the routing is done properly. This is due to common mode rejection, and the doubling of effective slew rate which improves switching performance at the REF CLK input stage.
If the clock source is very close to the DDS, then it is acceptable to use single-ended mode for the REF CLK. The performance of the DDS is about the same in either case. The performance issues depend on the length and quality of the routing of the REF CLK signal on the system board.
Q: Can I gate the REF CLK on and off?
A: Yes. This is a valid "sleep" strategy. Gating off the REF CLK between operating periods will significantly reduce the idling current.
The DDS logic is CMOS, and when it is not clocking, the current is greatly reduced. On the AD9858 (because the DAC is implemented in bipolar), the analog bias currents do not reduce when the ref clock is gated off.
Q: What is the effect of REF CLK jitter on the DDS?
A: REF CLK jitter will directly affect the DDS. The DDS output is sampled by the REF CLK, and therefore the REF CLK jitter determines the quality of the output signal. It directly affects the jitter characteristics of the DDS output.
If the REF CLK multiplier (PLL) is utilized, then the PLL (because its loop bandwidth acts as a bandpass filter) helps to filter out frequency components of the REF CLK that are outside of the loop bandwidth of the PLL. However, using the REF CLK multiplier will increase the effective noise on the REF CLK within the loop bandwidth of the PLL (typically a few hundred kHz). The increase of noise within the loop bandwidth will follow the formula of dB = 20log x, where x is the REF CLK multiplication value.
Packaging / Thermals
Q: Are there any specific recommendations for material in the vias of the circuit board for the thermally enhanced package styles in which some ADI DDSs are available?
A: The vias must be through-plated. Solder will suffice as a material (solder is much less expensive than silver-over-copper plate).
Q: I have limited experience working with thermally enhanced packages. Where can I get information concerning the proper techniques for soldering and assembly?
A: Please refer to AN-772, "A Design and Manufacturing Guide for the LFCSP". Information is also available on the package manufacturer's website (Amkor Technology: www.amkor.com). Look for: "Application Notes For Surface Mount Assembly of Amkor's Thermally / Electrically Enhanced Leadframe Based Packages."
Q: I need to operate my DDS part above the rated temperature range. Can you give me any reliability data?
A: No. The temperature range stated in the data sheet is the range over which the part has been qualified at ADI. Extended temperature range data is not available.
Q: Are any of your DDS products space qualified?
A: No.
Q: What kind of problems can I expect from exceeding the maximum clock rate? (power dissipation, spectral problems)
A: Typically, the first thing to happen when you exceed the maximum CLOCK RATE is a violation of the thermal specifications of the device. The increase in clock rate causes an increase in power dissipation which raises the die temperature. This temperature rise can be calculated by the following formula: Tdie = Tambient + PWR(Theta JA). You should not exceed the maximum junction temperature specification, which is typically 150C.
Overclocking also may result in spectral degradation, due to the violation of internal timing requirements (internal setup and hold times) which are thermally sensitive. If you over clock an ADI DDS part, you do so at your own risk. ADI does not guarantee performance or lifespan of the device.
Q: Why did the model numbers change on the AD9852 and AD9854 products? I thought they were available in the ASQ package.
A: The AD9852ASQ and AD9854ASQ have been replaced by the AD9852ASVZ and AD9854ASVZ, respectively. This change is required due to the obsolescence of the SQ-80 package at our subcontractor. The new SV-80 package types are pin for pin compatible with the footprint of the SQ-80.
- The data sheet will change to REQUIRE the exposed paddle on the SV-80 package be soldered to the circuit board for thermal reasons.
- The SV-80 package is slightly thinner (1.00 vs 1.40 nominal).
- The exposed paddle is square rather than octagonal, but roughly the same size.
The AD9852AST and AD9854AST packages are still available.
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