ADF4193:  Low Phase Noise, Fast Settling PLL

The ADF4193 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. Its architecture is specifically ...More

ADF4193:  Low Phase Noise, Fast Settling PLL

Product Description

The ADF4193 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations.

It consists of a low-noise digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier (Diff Amp) to convert the differential charge pump output to a single ended voltage for the external voltage controlled oscillator (VCO). The Σ-Δ based fractional interpolator, working with the N divider, allow programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler, allows selectable reference signal (REFIN) frequencies at the PFD input.

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This saves cost, complexity, PCB area, shielding and characterization on previous ping-pong GSM PLL architectures.

Features

  • New fast settling fractional-N PLL architecture
  • Frequency hop across the GSM band in 5 µs, phase settled by 20 µs
  • Single PLL replaces ping-pong synthesizers
  • 0.5 degree RMS phase error at 2 GHz RF output
  • Digitally programmable output phase
  • RF input range up to 3.5 GHz
  • On-chip low noise differential amplifier
  • Phase noise figure of merit –216 dBc/Hz
  • Loop filter design possible using ADI SimPLL

Diagrams

ADF4193 Diagram
Functional Block Diagram for ADF4193

Specifications

Type Fast Settling PLL
Max RF Input (MHz) 3500MHz
Norm Phase Noise (dBc/Hz) -216dBc
Max REFin (MHz) 300MHz
RF Prescalers 4/5,8/9
Package 32-Lead CSP

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ADF4106 Single Integer-N 6000 - -219 300 16/17, 32/33, 64/65, 8/9 13 16-Lead TSSOP, 20-Lead CSP $2.16
ADF4107 Single Integer-N 7000 - -219 250 16/17, 32/33, 64/65, 8/9 13 16-Lead TSSOP, 20-Lead CSP $2.67
ADF4108 Single Integer-N 8000 - -219 250 16/17, 32/33, 4/5, 64/65, 8/9 17 20-Lead CSP $3.34
ADF4110 Single Integer-N 550 - -215 104 16/17, 32/33, 64/65, 8/9 4.5 16-Lead TSSOP, 20-Lead CSP $2.28
ADF4111 Single Integer-N 1200 - -215 104 16/17, 32/33, 64/65, 8/9 4.5 16-Lead TSSOP, 20-Lead CSP $2.28
ADF4112 Single Integer-N 3000 - -215 104 16/17, 32/33, 64/65, 8/9 6.5 16-Lead TSSOP, 20-Lead CSP $2.28
ADF4113 Single Integer-N 4000 - -215 104 16/17, 32/33, 64/65, 8/9 8.5 16-Lead TSSOP, 20-Lead CSP $2.28
ADF4113HV Single Integer-N 4000 - -212 104 16/17, 32/33, 64/65, 8/9 11 16-Lead TSSOP, 20-Lead CSP $2.49
ADF4116 Single Integer-N 550 - -211 100 8/9 4.5 16-Lead TSSOP $2.28
ADF4117 Single Integer-N 1200 - -213 100 32/33 4.5 16-Lead TSSOP $2.28
ADF4118 Single Integer-N 3000 - -216 100 32/33 6.5 16-Lead TSSOP $2.28
ADF4153 Single Fractional-N 4000 - -213 250 4/5, 8/9 12 16-Lead TSSOP, 20-Lead CSP $2.28
ADF4154 Single Fractional-N 4000 - -213 250