ADCMP561: Dual High Speed PECL Comparator 16 - Lead QSOP
The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 1 ns propagation delay with less than 150 ps overdrive dispersion. ...More
For additional technical information and samples, pls contact the High Speed Comparators Group. Supply your name, company, mailing address, telephone/fax numbers, email address and a brief description of your application.
ADCMP561: Dual High Speed PECL Comparator 16 - Lead QSOP
Product Description
The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 1 ns propagation delay with less than 150 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP562.
A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from -2.0 V to +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 . to VDD - 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation.
The ADCMP561/ADCMP562 are specified over the industrial temperature range (-40°C to +85°C). The ADCMP561 is available in a 16-lead QSOP package. The ADCMP562 is available in a 20-lead QSOP package.
Features
- Differential PECL Compatible Outputs
- 1 ns Propagation Delay Input to Output
- 100 ps Propagation Delay Dispersion
- Input Common-Mode Range: –2.0 V to +3.0 V
- Input Differential Range
- Robust Input Protection
- Differential Latch Control
- Power Supply Rejection Greater Than 70 dB
- 700 ps Minimum Pulse Width
- 1.5 GHz Equivalent Input Rise Time Bandwidth
- Typical Output Rise/Fall Time of 500 ps
- Programmable Hysteresis
Diagrams
- Enlarge
- Другие диаграммы
- Обозначения и трафареты для печатной платы
Functional Block Diagram for ADCMP561
Dual High Speed PECL Comparator 16 - Lead QSOP
Другие диаграммы для ADCMP561
Dual High Speed PECL Comparator 16 - Lead QSOP
16-Lead QSOP Pin Configuration
Functional Block Diagram for ADCMP561
| Part# | Prop Delay (ns)typ | # Per Pkg | Total Power (mW) | Voltage Supply (V) | No of Supplies | Input Range (V) | Logic Output | Adjustable Hysteresis | Min Pulse Width |
|---|---|---|---|---|---|---|---|---|---|
| AD790 | 45 | 1 | 250 | +/-15 | 3 | -Vs to Vs -2V | TTL/CMOS | Fixed | - |
| AD8561 | 7 | 1 | 65 | +/- 5 | 2 | -5.0V to +3.0V | Diff/TTL | - | - |
| AD8564 | 8 | 4 | 150 | +/- 5 | 2 | -5.0V to +3.0V | TTL/CMOS | - | - |
| AD8611 | 5.5 | 1 | 50 | 3 to 5 | 1 | 0 to 3V | Diff/TTL | - | - |
| AD8612 | 5.5 | 2 | 100 | 3 to 5 | 1 | 0 to 3V | Diff/TTL | - | - |
| AD96685 | 6 | 1 | 120 | 5, -5.2 | 2 | -2.5V to +5.0V | Diff/ECL | - | - |
| AD96687 | 6 | 2 | 240 | 5, -5.2 | 2 | -2.5V to +5.0V | Diff/ECL | - | - |
| ADCMP551 | 0.75 | 2 | 60 | 3.3 to 5 | 1 | -0.2 to Vcc-2V | PECL | - | 700ps |
| ADCMP552 | 0.75 | 2 | 60 | 3.3 to 5 | 1 | -0.2 to Vcc-2V | PECL | X | 700ps |
| ADCMP553 | 0.75 | 1 | 30 | 3.3 to 5 | 1 | -0.2 to Vcc-2V | PECL | - | 700ps |
| ADCMP561 | 0.75 | 2 | 160 | 5, -5.2 | 2 | -2 to 3V | PECL | - | 700ps |
| ADCMP562 | 0.75 | 2 | 160 | 5, -5.2 | 2 | -2 to 3V | PECL | X | 700ps |
| ADCMP563 | 0.75 | 2 | 120 | 5, -5.2 | 2 | -2 to 3V | ECL | - | 700ps |
| ADCMP564 | 0.75 | 2 | 120 | 5, -5.2 | 2 | -2 to 3V | ECL | X | 700ps |
| ADCMP572 | 0.15 | 1 | 145 | 3.3 to 5 | 1 | -0.2 to Vcci-2.1V | CML | X | 80ps |
| ADCMP573 | 0.15 | 1 | 145 | 3.3 to 5 | 1 | -0.2 to Vcci-2.1V | PECL | X | 80ps |
| ADCMP580 | 0.15 | 1 | 240 | 5, -5.2 | 2 | -2 to 3V | CML | X | 80ps |
| ADCMP581 | 0.15 | 1 |

